Cascaded counter circuit with pipelined reload of variable ratio determined values

A computing system, comprising:

• a plurality of processing cores;
• a memory controller, said memory controller coupled to a system memory;
• a display;
• a counter circuit to count a value within said computer system, said counter circuit comprising ordered state element circuits where a respective clock input of a state element circuit of the ordered state element circuits is fed by a data output of a preceding lower ordered bit state element of the ordered state element circuits, said counter circuit also being programmable to enable different values to be counted by said counter circuit, wherein respective reload values for said values are received at said state element circuits as a respective asynchronous set or reset, said counter having an input that receives an input clock and an output that provides an output clock having a divided down frequency of said input clock, and wherein the ordered state element circuits toggle in phase along a same clock edge in response to a reload value that starts a next count sequence.