Dynamic multicycles for core-periphery timing closure

A method to synthesize logic circuitry to be implemented in a programmable logic device comprising:

• receiving a logic design;
• identifying a plurality of data transfers of the logic design, wherein each data transfer comprises a respective source memory element and a respective destination memory element;
• calculating, for each data transfer of the logic design, a respective clock skew based on a respective source latency of a clock signal received by the respective source memory element and a respective destination latency of a clock signal received by the respective destination memory element;
• assigning, for each data transfer, a respective launch edge of a clock signal received by the respective source memory element and a respective hold edge of a clock signal received by the respective destination memory element based on the respective clock skew;
• and
• programming the programmable logic device to perform at least the data transfer.

An article of manufacture, comprising instructions to cause a processor to:

• communicate with a programmable logic device that comprises a programmable fabric and fixed circuitry;
• receive a logic design, the logic design comprising at least one data transfer between a memory element in the programmable fabric and a memory element in the fixed circuitry;
• retrieve a latency information associated with the fixed circuitry from a file, a database, or any combination thereof;
• determine a multicycle constraint based on the latency information and the logic design;
• assign a launch edge and a hold edge of the data transfer based on the multicycle constraint;
• and
• program the programmable logic device.