Pulse-width modulation (PWM) control loop for power application

A programmable logic device (PLD) comprising:

• a power transistor;
• a programmable fabric;
• a memory block including one or more lookup tables storing pre-calculated data;
• and
• a signal wrapper providing signals between the programmable fabric and the memory block;
• wherein the pre-populated data stored in the one or more lookup tables of the memory block is programmably changed by programming the programmable fabric and loading the pre-populated data to the one or more lookup tables via the signal wrapper,
• wherein the memory block is configured to receive an error signal from the signal wrapper, look up a matching pre-calculated data corresponding to the error signal, and generate a compensated output signal using the matching pre-calculated data, and
• wherein the compensated output signal is a pulse width of a pulse-width modulation (PWM) signal for driving the power transistor.