Dynamic decode circuit with active glitch control method
AssigneeInternational Business Machines Corporation
InventorsPaul Alan Bunce, Yuen Hung Chan, John D Davis, Antonio Raffaele Pelella
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Abstract
A method for decoding a plurality of input signals in a plurality of dynamic decode circuits, each dynamic decode circuit sharing a conditioned node and comprising a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate.
Claims19
A method for conditioning a shared node of a plurality of dynamic decode circuits, each dynamic decode circuit having a decoder, an output transistor and a conditioning transistor, each conditioning transistor of the plurality of dynamic decode circuits connected in parallel between a common power source and the shared node, the each dynamic decode circuit performing, the method comprising:
- receiving input signals, by a plurality of inputs of the decoder;
- precharging a first node of the decoder to a high state, by a first precharge circuit comprising a first precharge transistor, based on being in a precharge phase of an evaluation clock, the first node being conductively connected to a gate of the output transistor;
- precharging a second node of the output transistor to the high state, by a second precharge circuit comprising a second precharge transistor, based on being in the precharge phase of the evaluation clock, the output transistor being disposed between the second node and an interconnecting node;
- pulling a third node of the decoder to a low state, by an evaluate transistor, based on being in an evaluation phase of the evaluation clock;
- pulling the interconnecting node of the output transistor to the low state, by the evaluate transistor, based on being in the evaluation phase of the evaluation clock, wherein the third node and the interconnecting node of the decoder are pulled to the low state, by the evaluate transistor, based on being in the evaluation phase of the evaluation clock;
- based on the plurality of inputs being in a predetermined state, causing the first node to be in the high state;
- and
- based on the plurality of inputs not being in the predetermined state, causing the first node to be in the low state;
- based on the first node being in the high state during the evaluation phase of the evaluation clock, causing the second node of the output transistor to be in the low state;
- and
- based on the first node being in the low state during the evaluation phase of the evaluation clock, causing the second node of the output transistor to be in the high state;
- and
- causing, by the conditioning transistor, the shared node to be in a conditioned state, wherein the conditioning transistor consists of any one of a precharge transistor of the precharge circuit and the evaluation transistor.
A method for conditioning a shared node of a plurality of dynamic decode circuits, each dynamic decode circuit having a decoder, an output transistor and a conditioning transistor, each conditioning transistor of the plurality of dynamic decode circuits connected in parallel between a common power source and the shared node, the each dynamic decode circuit performing the method comprising:
- receiving input signals, by a plurality of inputs of the decoder;
- precharging a first node of the decoder to a high state, by a first precharge circuit comprising a first precharge transistor, based on being in a precharge phase of an evaluation clock, the first node being conductively connected to a gate of the output transistor;
- precharging a second node of the output transistor to the high state, by a second precharge circuit comprising a second precharge transistor, based on being in the precharge phase of the evaluation clock, the output transistor being disposed between the second node and an interconnecting node;
- pulling a third node of the decoder to a low state, by a first evaluate transistor, based on being in an evaluation phase of the evaluation clock;
- pulling the interconnecting node of the output transistor to the low state, by a second evaluate transistor, based on being in the evaluation phase of the evaluation clock;
- based on the plurality of inputs being in a predetermined state, causing the first node to be in the high state;
- and
- based on the plurality of inputs not being in the predetermined state, causing the first node to be in the low state;
- based on the first node being in the high state during the evaluation phase of the evaluation clock, causing the second node of the output transistor to be in the low state;
- and
- based on the first node being in the low state during the evaluation phase of the evaluation clock, causing the second node of the output transistor to be in the high state;
- and
- causing, by the conditioning transistor, the shared node to be in a conditioned state, wherein the conditioning transistor consists of a precharge transistor of the precharge circuit.
Dependencies are inferred from the claim text.