Programmable pipeline interface circuit

A circuit arrangement, comprising:

• a plurality of blocks of programmable logic circuitry, wherein each block of programmable logic circuitry is configurable to implement a logic function;
• programmable interconnect circuitry that is configurable to selectively route signals between the plurality of blocks of programmable logic;
• a plurality of interface circuits coupled to the plurality of blocks of programmable logic circuitry, respectively, wherein each interface circuit includes:
• a first plurality of bi-stable circuits, each bi-stable circuit of the first plurality having a data input, a clock input, and an output coupled to the respective block of programmable logic circuitry;
• control circuitry coupled to the first plurality of bi-stable circuits, wherein the control circuitry is programmable to:
• receive an input clock signal;
• selectively connect, responsive to a first plurality of control signals, outputs of the first plurality of bi-stable circuits or signals at the data inputs of the plurality of bi-stable circuits to inputs of the respective block of programmable logic circuitry,
• generate one or more delayed clock signals from the input clock signal, and
• selectively provide, responsive to a second plurality of control signals, one of the one or more delayed clock signals or the input clock signal without delay to the clock input of each of the first plurality of bi-stable circuits.