Frequency divider with selectable frequency and duty cycle

A frequency divider system comprising:

• a split-divisor frequency divider module that receives a clock signal and generates an output signal based on a first divisor and a second divisor, the clock signal and output signal each having rectangular waveforms characterized by a respective frequency and pulse width;
• wherein:
• the frequency of the output signal is a selectable integer fraction of the frequency of the clock signal, the frequency of the output signal being selected based on a sum of the first and second divisors;
• the pulse width of the output signal is a selectable integer number of clock cycles of the clock signal, the pulse width of the output signal being selected based on at least one of the first divisor and the second divisor;
• a fractional pulse width adjuster module, the fractional pulse width adjuster module is configured to adjust the pulse width of a split-divisor frequency divider module output signal by a fraction of an input clock cycle;
• and
• a high frequency bypass module, the high frequency bypass module configured to bypass one or more stages of the frequency divider,
• wherein the split-divisor frequency divider module comprises:
• a selector module configured to select between the first and second divisors based on a control input, the control input being coupled to the output signal of the split-divisor frequency divider module;
• an integer divider configured to generate pulses every N2 clock cycles, where N2 is set to one of the first and second divisors selected by the selector module;
• and
• a toggle module configured to toggle the output signal at each low-to-high or high-to-low transition of the pulses generated by the integer divider.