US 10,320,369 B2Granted

Sequential circuits and operating methods thereof

AssigneeSamsung Electronics Co., Ltd.

InventorsHyunchul Hwang, Minsu Kim

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Abstract

In a sequential circuit, a first stage is configured to charge a voltage of a first node in response to a clock, and to discharge the voltage of the first node in response to the clock, a voltage of a second node, and data; a second stage is configured to charge the voltage of the second node in response to the clock, and to discharge the voltage of the second node in response to the clock and a logic signal; a combinational logic is configured to generate the logic signal based on the voltage of the first node, the voltage of the second node, and the data; and a latch circuit is configured to latch the voltage of the second node in response to the clock.

Claims20

Dependent claims

A sequential circuit, comprising:

a first stage configured to charge a voltage of a first node in response to a clock and to discharge the voltage of the first node in response to the clock and a logic signal;
a second stage configured to charge a voltage of a second node in response to the clock and to maintain a state of charge at the second node based on the logic signal and to discharge the voltage of the second node in response to the clock and the logic signal;
a combinational logic configured to generate the logic signal using the voltage of the first node, the voltage of the second node, and data;
and
a latch circuit configured to latch the voltage of the second node in response to the clock,
wherein the combinational logic generates the logic signal such that the voltage of the second node is not discharged when the voltage of the first node is discharged or such that the voltage of the first node is not discharged when the voltage of the second node is discharged.

3 more elements

A sequential circuit, comprising:

a first stage comprising:
a first PMOS transistor having one end connected to a first node in response to a clock,
a second PMOS transistor configured to connect the first node to a power supply terminal in response to a voltage of a second node,
a third PMOS transistor configured to connect other end of the first PMOS transistor to the power supply terminal in response to a scan input,
a fourth PMOS transistor configured to connect the one end of the first PMOS transistor to the power supply terminal in response to a scan enable signal,
a first NMOS transistor configured to connect a first connection node to the first node in response to the clock,
a second NMOS transistor having one end connected to the first node in response to the scan input, and
a third NMOS transistor configured to connect a second connection node to other end of the second NMOS transistor in response to the scan enable signal;
a second stage comprising:
a first PMOS transistor configured to connect the second node to the power supply terminal in response to the clock,
a second PMOS transistor configured to connect the second node to the power supply terminal in response to a logic signal,
a first NMOS transistor connected to the second node in response to the logic signal, and
a second NMOS transistor configured to connect a ground terminal to other end of the first NMOS transistor of the second stage in response to the clock;
a combinational logic configured to receive data, the voltage of the first node, and the voltage of the second node and to generate the logic signal, wherein an output terminal of the combinational logic outputting the logic signal is connected to the first connection node;
and
a latch circuit configured to latch the voltage of the second node in response to the clock.

13 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/903,507Filed 23 Feb 2018 · continuation in part
Priority: KR 10-2015-01264207 Sep 2015
Published: US 2018/0183415 A128 Jun 2018
Granted: 11 Jun 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H03K 3/356121
Using additional transistors in the input circuit: with synchronous operation
G11C 11/4074
For memory cells of the field-effect type: power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage…
G11C 19/28
Digital stores in which the information is moved stepwise, e.g. shift registers: using semiconductor elements
G11C 27/02
Electric analogue stores, e.g. for storing instantaneous values: sample-and-hold arrangements

Family

Application15/254,272Parent of this continuation-in-part · filed 1 Sep 2016
US 2018/0183415 A1Pre-grant publication · published 28 Jun 2018
US 10,038,428 B2Parent of this continuation-in-part
US 2017/0070215 A1Published application
US 10,320,369 B2This patent

From the US filing history. Foreign family members aren’t listed.

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