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US 10,320,368 B2Granted
Ring oscillator circuit and clock signal generation circuit
AssigneeSeiko Epson Corporation
InventorKoichi Hatanaka
Life of this patent
Estimating the term…
Abstract
A ring oscillator circuit includes a plurality of first delay circuits each including X first delay elements, and a second delay circuit including a plurality of second delay elements different in delay amount from each other arranged in parallel to each other so as to be alternatively loaded, the plurality of first delay circuits and the second delay circuit are configured to be connected to each other in a ring-like manner, and X is an integer fulfilling X≥1.
Claims11
A ring oscillator circuit comprising:
- a plurality of first delay circuits each including X first delay elements;
- a second delay circuit including a plurality of second delay elements different in delay amount from each other arranged in parallel to each other so as to be alternatively loaded,
- wherein the plurality of first delay circuits and the second delay circuit are configured to be connected to each other in a ring-like manner, and
- X is an integer fulfilling X≥1;
- and
- a plurality of switches, each of the plurality of switches having a first node and a second node,
- wherein the first node of each of the plurality of switches is connected to an output of each first delay circuit in a subset of the plurality of first delay circuits, and the second node of each of the plurality of switches is connected to an input of the each of the plurality of second delay circuits.
4 more elements
A ring oscillator circuit comprising:
- a plurality of first delay circuits each including X first delay elements;
- a second delay circuit including a plurality of second delay elements different in delay amount from each other arranged in parallel to each other so as to be alternatively loaded,
- wherein the plurality of first delay circuits and the second delay circuit are configured to be connected to each other in a ring-like manner, and
- X is an integer fulfilling X≥1;
- a plurality of first switches, each of the plurality of first switches having a first node and a second node,
- wherein the first node of each of the plurality of first switches is connected to an output of each first delay circuit in a subset of the plurality of first delay circuits, and the second node of each of the plurality of switches is connected to an input of the each of the plurality of second delay circuits;
- and
- a plurality of second switches, each of the plurality of second having a first node and a second node,
- wherein the first node of each of the plurality of second switches is connected to an input of a first delay circuit of the plurality of first delay circuits, and the second node of each of the plurality of second switches is connected to an input of each of the plurality of second delay circuits.
6 more elements
Dependencies are inferred from the claim text.