Vertical memory device

A vertical memory device comprising:

• a plurality of gate electrode layers stacked in a cell region of a semiconductor substrate;
• a plurality of upper isolation insulating layers dividing an uppermost gate electrode layer among the plurality of gate electrode layers into a plurality of regions electrically isolated from each other, the plurality of upper isolation insulating layers being disposed in a plurality of trenches extending in a first direction and be spaced apart from each other;
• a plurality of vertical holes comprising:
• a plurality of channel holes penetrating through the plurality of gate electrode layers, the plurality of channel holes being disposed between the plurality of upper isolation insulating layers, and
• a plurality of first support holes penetrating through at least a portion of the plurality of upper isolation insulating layers, wherein any two adjacent vertical holes of the plurality of vertical holes have a uniform distance from each other throughout the cell region;
• a plurality of channel structures disposed in the plurality of channel holes;
• and
• a plurality of first support structures disposed in the plurality of first support holes,
• wherein the plurality of channel holes and the plurality of first support holes have a same diameter, and the plurality of channel structures include materials different from the plurality of first support structures.