Insulated gate bipolar transistor and fabrication method thereof

An insulated gate bipolar transistor, comprising:

• a semiconductor layer, including a collector electrode layer and a bulk layer on the collector electrode layer, wherein the semiconductor layer has a cell region and an edge region around the cell region, and the cell region includes a first region and a second region around the first region;
• a well region, in the bulk layer associated with the cell region;
• a drift region, in the bulk layer associated with the cell region, wherein the drift region is formed between the well region and the collector electrode layer, and a conductivity type of the drift region is respectively opposite to conductivity types of the well region and the collector electrode layer;
• a plurality of gate structures, in the bulk layer associated with the cell region, wherein each gate structure penetrates through the well region and extends into the drift region;
• source and drain doped regions, in a top region of the well region on both sides of each gate structure, wherein a conductivity type of the source and drain doped regions is opposite to the conductivity type of the well region, and a size of the source and drain doped regions in the second region is smaller than a size of the source and drain doped regions in the first region;
• and
• an ohmic contact region, in the top region of the well region, wherein the source and drain doped regions are formed between each gate structure and the ohmic contact region, a conductivity type of the ohmic contact region is the same as the conductivity type of the well region, and a size of the ohmic contact region in the second region is larger than a size of the ohmic contact region in the first region, wherein:
• the size of the source and drain doped regions in the second region progressively decreases along a direction from the cell region to the edge region;
• and
• the size of the ohmic contact region in the second region progressively increases along the direction from the cell region to the edge region.

A method for fabricating an insulated gate bipolar transistor, comprising:

• providing a semiconductor layer, including a collector electrode layer and a bulk layer on the collector electrode layer, wherein the semiconductor layer has a cell region and an edge region around the cell region, and the cell region includes a first region and a second region around the first region;
• forming a well region, a drift region, and a plurality of gate structures, in the bulk layer associated with the cell region, wherein the drift region is formed between the well region and the collector electrode layer, a conductivity type of the drift region is respectively opposite to conductivity types of the well region and the collector electrode layer, and each gate structure penetrates through the well region and extends into the drift region;
• and
• forming source and drain doped regions and an ohmic contact region, in a top region of the well region, wherein the source and drain doped regions are formed on both sides of each gate structure and between the gate structure and the ohmic contact region, a conductivity type of the source and drain doped regions is opposite to the conductivity type of the well region, a size of the source and drain doped regions in the second region is smaller than a size of the source and drain doped regions in the first region, a conductivity type of the ohmic contact region is the same as the conductivity type of the well region, and a size of the ohmic contact region in the second region is larger than a size of the ohmic contact region in the first region.