High voltage transistor using buried insulating layer as gate dielectric

A transistor element, comprising:

• a channel region positioned between a drain region and a source region;
• a portion of a buried insulating layer positioned below at least said channel region;
• a doped semiconductor region positioned below said portion of said buried insulating layer and connected to a control terminal, said portion of said buried insulating layer and said doped semiconductor region forming a gate electrode structure;
• and
• an interlayer dielectric material laterally extending continuously between said drain region and said source region across an entire height of said drain region and said source region.

A method, comprising:

• forming a gate electrode structure of a transistor element by doping a portion of a substrate material of a semiconductor substrate below a portion of a buried insulating layer;
• forming a drain region and a source region on a semiconductor layer formed on said buried insulating layer;
• and
• forming an interlayer dielectric material laterally extending continuously between said drain region and said source region across an entire height of said drain region and said source region.