US 10,319,824 B2Granted

Semiconductor device includes a substrate having a bandgap wider than that of silicon and method of manufacturing semiconductor device

AssigneeFuji Electric Co., Ltd.

InventorsMakoto Utsumi, Akimasa Kinoshita, Yasuhiko Oonishi

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Abstract

A MOS gate is provided on a front surface side of a silicon carbide substrate. The silicon carbide substrate includes silicon carbide layers sequentially formed on an n+-type starting substrate by epitaxial growth. Of the silicon carbide layers, a p+-type silicon carbide layer is a p+-type high-concentration base region and is separated into plural regions by a trench. A p-type silicon carbide layer among the silicon carbide layers covers the p+-type silicon carbide layer and is embedded in the trench. A p-type silicon carbide layer among the silicon carbide layers is a p-type base region. From a substrate front surface, a gate trench penetrates the p-type base region in the trench and the n+-type source region to reach an n−-type drift region. Between the p+-type high-concentration base region and a gate insulating film at a sidewall of the gate trench, the p-type base region is embedded in the trench.

Claims11

Dependent claims

A semiconductor device comprising:

a semiconductor substrate containing a wide bandgap semiconductor material having a bandgap wider than that of silicon;
a first semiconductor layer of a first conductivity type provided on a front surface of the semiconductor substrate and containing the wide bandgap semiconductor material;
a second semiconductor layer of a second conductivity type provided on a surface on a first side of the first semiconductor layer opposite a second side of the first semiconductor layer facing the semiconductor substrate, the second semiconductor layer containing the wide bandgap semiconductor material;
a first groove penetrating both surfaces of the second semiconductor layer in a thickness direction and reaching the first semiconductor layer wherein the first groove extends to the surface of the first semiconductor layer on the first side thereof;
a third semiconductor layer of the second conductivity type provided on a surface on a first side of the second semiconductor layer opposite a second side of the second semiconductor layer facing the first semiconductor layer, the third semiconductor layer lining the first groove, an impurity concentration of the third semiconductor layer lower than that of the second semiconductor layer, the third semiconductor layer containing the wide bandgap semiconductor material;
a first semiconductor region of the first conductivity type selectively provided in the third semiconductor layer;
a trench penetrating, in the thickness direction, the third semiconductor layer in the first groove and the first semiconductor region to reach the first semiconductor layer, a width of the trench narrower than that of the first groove;
a gate insulating film provided along an inner wall of the trench;
a gate electrode provided on the gate insulating film in the trench;
a first electrode electrically connected to the first semiconductor region and the third semiconductor layer;
and
a second electrode electrically connected to a rear surface of the semiconductor substrate.

9 more elements

A method of manufacturing a semiconductor device, the method comprising:

depositing a first epitaxial layer of a first conductivity type on a front surface of a semiconductor substrate containing a semiconductor material having a bandgap wider than that of silicon;
depositing a second epitaxial layer of a second conductivity type on the first epitaxial layer;
forming a first groove penetrating both surfaces of the second epitaxial layer in a thickness direction and reaching the first epitaxial layer wherein the first groove extends to a surface of the first epitaxial layer without penetrating the first epitaxial layer;
depositing a third epitaxial layer of the second conductivity type on the second epitaxial layer and in the first groove, an impurity concentration of the third epitaxial layer lower than that of the second epitaxial layer;
selectively forming a first semiconductor region of the first conductivity type in the third epitaxial layer;
forming a trench penetrating, in the thickness direction, the first semiconductor region and the third epitaxial layer in the first groove and reaching the first epitaxial layer, a width of the trench narrower than that of the first groove;
forming a gate insulating film along an inner wall of the trench;
forming a gate electrode on the gate insulating film in the trench;
forming a first electrode on the first semiconductor region and electrically connected to the first semiconductor region and the third epitaxial layer;
and
forming a second electrode electrically connected to a rear surface of the semiconductor substrate.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/716,919Filed 27 Sep 2017
Priority: JP 2016-1976085 Oct 2016
Published: US 2018/0097079 A15 Apr 2018
Granted: 11 Jun 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10D 64/513
Disposition of the gate electrodes, e.g. buried gates: within recesses in the substrate, e.g. trench gates, groove gates or buried gates
H10D 12/031
Manufacture or treatment: of igbts
H10D 12/038
Of vertical IGBTs: having a recessed gate, e.g. trench-gate IGBTs
H10D 12/481
Having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions: having gate…

Family

US 2018/0097079 A1Pre-grant publication · published 5 Apr 2018
US 10,319,824 B2This patent

From the US filing history. Foreign family members aren’t listed.

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