Self-aligned gate edge and local interconnect and method to fabricate same

A method of fabricating and integrated circuit structure, the method comprising:

• forming a first fin having a longest dimension along a first direction;
• forming a second fin having a longest dimension along the first direction;
• forming a first gate structure over the first fin, the first gate structure having a longest dimension along a second direction, the second direction orthogonal to the first direction;
• forming a second gate structure over the second fin, the second gate structure having a longest dimension along the second direction, the second gate structure discontinuous with the first gate structure along the second direction, and the second gate structure having an edge facing an edge of the first gate structure along the second direction;
• forming a gate edge isolation structure between and in contact with the edge of the first gate structure and the edge of the second gate structure along the second direction, the gate edge isolation structure having a length along the first direction greater than a length of the first gate structure and the second gate structure along the first direction;
• and
• forming a dielectric material laterally adjacent to and in contact with the gate edge isolation structure, and the dielectric material having a composition different than a composition of the gate edge isolation structure.

A method of fabricating an integrated circuit structure, the method comprising:

• forming a first fin comprising silicon, the first fin having a longest dimension along a first direction;
• forming a second fin comprising silicon, the second fin having a longest dimension along the first direction;
• forming an isolation material between the first fin and the second fin;
• forming a first gate structure over the first fin, the first gate structure having a longest dimension along a second direction, the second direction orthogonal to the first direction, wherein the first gate structure comprises a first gate dielectric layer and a first gate electrode;
• forming a second gate structure over the second fin, the second gate structure having a longest dimension along the second direction, the second gate structure discontinuous with the first gate structure along the second direction, and the second gate structure having an edge facing an edge of the first gate structure along the second direction, wherein the second gate structure comprises a second gate dielectric layer and a second gate electrode;
• forming a gate edge isolation structure between and in contact with the edge of the first gate structure and the edge of the second gate structure along the second direction, the gate edge isolation structure over the isolation material;
• and
• forming a dielectric material laterally adjacent to the first and second gate structures along the first direction, the dielectric material laterally adjacent to the gate edge isolation structure along the first direction, and the dielectric material discrete from the gate edge isolation structure.