Memory device and memory system
AssigneeSony Semiconductor Solutions Corporation
InventorHaruhiko Terada
Life of this patent
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AssigneeSony Semiconductor Solutions Corporation
InventorHaruhiko Terada
Estimating the term…
Provided is a memory device that has a structure suitable for still higher integration while securing production easiness, and includes n memory cell units stacked, on a substrate, in order as first to n-th memory cell units in a first direction. The n memory cell units each include: one or more first electrodes; a plurality of second electrodes each provided to intersect the first electrode; a plurality of memory cells provided at respective intersections of the first electrode and the second electrodes and each coupled to both the first and second electrodes; and one or more lead lines coupled to the first electrode to form one or more coupling parts, which, in (m+1)-th memory cell unit, are located at a position where the coupling parts and m-th memory cell region surrounded by the memory cells in m-th memory cell unit overlap each other in the first direction.
A memory device comprising
A memory system comprising:
Dependencies are inferred from the claim text.