Display substrate, its manufacturing method and display device

A method for manufacturing a display substrate, comprising a step of forming a plurality of thin film transistors (TFTs), wherein the method further comprises steps of:

• forming a lattice matching layer on a substrate so as to deposit aluminum nitride (AlN) on the lattice matching layer;
• depositing an AlN layer on the lattice matching layer by low-temperature pulse magnetron sputtering;
• and
• forming on the AlN layer gallium nitride (GaN) light-emitting diodes (LEDs) each including an n-type GaN layer, a multilayered quantum well structure and a p-type GaN layer and corresponding to one of the TFTs,
• wherein the lattice matching layer is a graphene layer;
• wherein the step of forming the lattice matching layer on the substrate comprising:
• providing a base substrate;
• depositing a first transparent conductive layer on the base substrate;
• and
• forming the graphene layer on the first transparent conductive layer,
• the step of depositing the AlN layer on the lattice matching layer by low-temperature pulse magnetron sputtering comprises:
• depositing the AlN layer onto the graphene layer by low-temperature pulse magnetron sputtering,
• the step of forming on the AlN layer the GaN LEDs each including the n-type GaN layer, the multilayered quantum well structure and the p-type GaN layer comprises:
• forming the n-type GaN layer, a pixel definition layer, the multilayered quantum well structure, the p-type GaN layer and a second transparent conductive layer sequentially on the AlN layer;
• etching the pixel definition layer, the multilayered quantum well structure, the p-type GaN layer and the second transparent conductive layer at a channel region, so as to expose the n-type GaN layer at the channel region;
• etching the n-type GaN layer, the AlN layer and the graphene layer at the channel region, so as to form a first electrode hole penetrating through the n-type GaN layer, the AlN layer and the graphene layer;
• and
• forming a first electrode configured to connect the n-type GaN layer to the first transparent conductive layer through the first electrode hole, and
• the step of forming the plurality of TFTs comprises:
• forming a planarization layer, and forming the TFT including a gate electrode, a gate insulation layer, a source electrode and a drain electrode on the planarization layer;
• forming a second electrode hole penetrating through the gate insulation layer and the planarization layer;
• forming a second electrode configured to connect the p-type GaN layer to the drain electrode through the second electrode hole;
• and
• forming a passivation layer.