Method for manufacturing image capturing device and image capturing device

A method for manufacturing an image capturing device having a photoelectric conversion region, a transfer transistor and a first peripheral transistor, comprising the steps of:

• (a) defining a pixel region and a peripheral region by forming an element isolation insulating film in a semiconductor substrate;
• (b) forming a transfer gate electrode of the transfer transistor in the pixel region and forming a first peripheral gate electrode of the first peripheral transistor in the peripheral region;
• (c) forming the photoelectric conversion region in a portion of the pixel region on one side of the transfer gate electrode;
• (d) forming a first insulating film so as to cover the pixel region and the peripheral region;
• (e) forming a first resist pattern over the first insulating film so as to cover the pixel region;
• (f) performing anisotropic etching of the first insulating film to form respective offset spacers on opposite side surfaces of the first peripheral gate electrode;
• (g) removing the first resist pattern;
• (h) forming respective first extension diffusion regions in the peripheral region on the opposite side surface sides of the first peripheral gate electrode by implanting an impurity of a predetermined conductivity type using the first peripheral gate electrode and the offset spacers as an implantation mask;
• (i) removing the first insulating film on the photoelectric conversion region while protecting the peripheral region to leave the offset spacers by performing a wet etching process;
• (j) forming a second insulating film so as to cover the pixel region and the peripheral region;
• (k) forming a second resist pattern over the second insulating film so as to cover the photoelectric conversion region;
• (l) performing anisotropic etching of the second insulating film to form respective sidewall spacers interposing the offset spacers on the opposite side surfaces of the first peripheral gate electrode;
• (m) removing the second resist pattern;
• (n) after the step (m), forming source-drain regions in the peripheral region on the opposite side surface sides of the first peripheral gate electrode by implanting an impurity of a predetermined conductivity type using the first peripheral gate electrode, the offset spacers and the sidewall spacers as an implantation mask.