Array substrate and method for making same

An array substrate comprising:

• a substrate, the substrate defining a display area and a peripheral area around the display area;
• a first insulator layer, the first insulator layer formed on the substrate and extending from the display area to the peripheral area;
• a second insulator layer, the second insulator layer formed on the first insulator layer and extending from the display area to the peripheral area;
• a third insulator layer, the third insulator layer formed on the second insulator layer and extending from the display area to the peripheral area;
• a first TFT, the first TFT formed on the substrate and positioned in the peripheral area, the first TFT comprising a first channel layer on the substrate, a first gate electrode on the first insulator layer, a first source electrode, and a first drain electrode, the first source electrode and the first drain electrode on the third insulator layer;
• a storage capacitance layer formed on the substrate;
• a second TFT, the second TFT formed on the substrate and positioned in the display area, the second TFT comprising a second gate electrode on the first insulator layer, a second channel layer on the second insulator layer, a second source electrode, and a second drain electrode, the second source electrode and the second drain electrode on the third insulator layer;
• and
• a third TFT, the third TFT formed on the substrate and positioned in the display area, the third TFT comprising a third gate electrode on the first insulator layer, a third channel layer on the second insulator layer, a third source electrode, and a third drain electrode, the third source electrode and the third drain electrode on the third insulator layer and electrically coupled to the third channel layer;
• the first insulator layer covering the first channel layer and the storage capacitance layer;
• the second insulator layer covering the first gate electrode, the second gate electrode, and the third electrode;
• wherein the first channel layer and the storage capacitance layer are made of a semiconducting material containing polycrystalline silicon;
• the second channel layer and the third channel layer are made of a semiconducting material containing metal oxide;
• the third insulator layer covers the second channel layer;
• a second source hole and a second drain hole are defined to overlap the second channel layer and extend through the third insulator layer;
• a third source hole and a third drain hole are defined to extend through the third insulator layer and overlap the third channel layer;
• a portion of the third insulator layer between the second drain hole and the second source hole defines a first protection portion;
• a portion of the third insulator layer between the third drain hole and the third source hole defines a second protection portion;
• wherein a first source hole and a first drain hole are defined to extend through the third insulator layer, the second insulator layer, and the first insulator layer, and overlap the first channel layer;
• the first source electrode extends into the first source hole to electrically couple to the first channel layer;
• the first drain electrode extends into the first drain hole to electrically couple to the first channel layer;
• a storage capacitance hole is defined to extend through the third insulator layer, the second insulator layer, and the first insulator layer, and overlap the storage capacitance layer;
• the second source electrode extends into the second source hole to electrically couple to the second channel layer;
• the second drain electrode extends into the second drain hole to electrically couple to the second channel layer;
• and
• the second drain electrode also extends into the storage capacitance hole to electrically couple to the storage capacitance layer.