Array substrate, fabricating method for the same and display device

A method for fabricating an array substrate, comprising:

• forming a patterned transparent electrode layer on a base substrate by using a first photo-mask process, wherein the transparent electrode layer comprises a data line, a source electrode, a drain electrode and a pixel electrode;
• the source electrode and the drain electrode are located in a transistor region and the data lines are electrically connected to the drain electrode, the pixel electrode is located in the pixel region and electrically connected to the source electrode;
• depositing the copper metal layer on the data line and the drain electrode by using an electroplating process;
• forming a patterned semiconductor active layer on the base substrate by using a second photo-mask process;
• the semiconductor active layer is formed between the source electrode and the drain electrode and respectively connected to the source electrode and the drain electrode;
• depositing a gate insulating layer on the base substrate, the gate insulating layer covering the transparent electrode layer, the copper metal layer and the semiconductor active layer;
• forming a patterned gate line and a gate electrode on the gate insulating layer by using a third photo-mask process, the gate electrode and the semiconductor active layer have overlapping portions.

A display device comprising an array substrate, comprising a pixel structure formed on a substrate, the pixel structure being provided with a transistor area and a pixel area, wherein the pixel structure comprises:

• a transparent electrode layer comprising a data line, a source electrode, a drain electrode and a pixel electrode, wherein the source electrode and the drain electrode being located in the transistor region and insulated from each other, the data line being electrically connected to the drain electrode, the pixel electrode being located in the pixel region and electrically connected to the source electrode;
• a copper metal layer deposited on the data line and the drain electrode;
• a semiconductor active layer formed between the source electrode and the drain electrode and respectively connecting to the source electrode and the drain electrode;
• a gate insulating layer overlying the transparent electrode layer, the copper metal layer and the semiconductor active layer;
• a gate line and a gate electrode electrically connected with each other are formed on the gate insulating layer, and the gate electrode and the semiconductor active layer overlap each other.