Array substrate, display panel, and display apparatus

A display panel, comprising an array substrate including:

• a plurality of pixels including sub-pixels forming a matrix, each sub-pixel including a pair of sub-pixel portions of domains of the each sub-pixel;
• a plurality of data lines;
• a plurality of gate lines intersecting with the plurality of data lines;
• and
• a plurality of pairs of transistors configured to control the plurality of pairs of sub-pixel portions;
• wherein:
• each pair of transistors are disposed adjacent to an intersection between a gate line and a data line, across at least one of the gate line or the data line, and are configured to control a pair of sub-pixel portions in neighboring rows or columns of sub-pixel portions;
• each of the plurality of sub-pixels comprises two pixel electrodes corresponding to the pair of sub-pixel portions;
• the pair of sub-pixel portions form a dual-domain configuration;
• the two pixel electrodes are insulated from one another, and have opposite domain tilt directions;
• the plurality of data lines alternate with the plurality of columns of sub-pixel portions such that one data line is arranged between two neighboring columns of sub-pixel portions;
• and
• one gate line is arranged between two rows of sub-pixel portions.

A display apparatus, comprising a display panel having an array substrate, the array substrate comprising:

• a plurality of pixels including sub-pixels forming a matrix, each sub-pixel including a pair of sub-pixel portions of domains of the each sub-pixel;
• a plurality of data lines;
• a plurality of gate lines intersecting with the plurality of data lines;
• and
• a plurality of pairs of transistors configured to control the plurality of pairs of sub-pixel portions;
• wherein:
• each pair of transistors are disposed adjacent to an intersection between a gate line and a data line, across at least one of the gate line or the data line, and are configured to control a pair of sub-pixel portions in neighboring rows or columns of sub-pixel portions;
• each of the plurality of sub-pixels comprises two pixel electrodes corresponding to the pair of sub-pixel portions;
• the pair of sub-pixel portions form a dual-domain configuration;
• the two pixel electrodes are insulated from one another, and have opposite domain tilt directions;
• the plurality of data lines alternate with the plurality of columns of sub-pixel portions such that one data line is arranged between two neighboring columns of sub-pixel portions;
• and
• one gate line is arranged between two rows of sub-pixel portions.