US 10,319,740 B2Granted

Memory device and method for manufacturing memory device

AssigneeToshiba Memory Corporation

InventorYasuhito Yoshimizu

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Abstract

A memory device includes first and second conductive layers, first and second semiconductor members, first and second charge storage members, first and second insulating members, and first and second insulating layers. The second conductive layer is distant from the first conductive layer. The first semiconductor member is positioned between the first and second conductive layers. The second semiconductor member is positioned between the first semiconductor member and the second conductive layer. The first insulating layer includes a first region positioned between the first semiconductor member and the first charge storage member and a second region positioned between the first semiconductor member and the second semiconductor member. The second insulating layer includes a third region positioned between the second semiconductor member and the second charge storage member and a fourth region positioned between the second region and the second semiconductor member.

Claims20

Dependent claims

A memory device comprising:

a first conductive layer extending along a first direction;
a second conductive layer being distant from the first conductive layer in a second direction crossing the first direction and extending along the first direction;
a first semiconductor member extending in a third direction crossing a plane including the first direction and the second direction, and passing through between the first conductive layer and the second conductive layer;
a second semiconductor member extending in the third direction and passing through between the first semiconductor member and the second conductive layer;
a first charge storage member provided between the first conductive layer and the first semiconductor member;
a first insulating member provided between the first conductive layer and the first charge storage member;
a first insulating layer including a first region and a second region, the first region being positioned between the first semiconductor member and the first charge storage member, the second region being positioned between the first semiconductor member and the second semiconductor member;
a second charge storage member provided between the second conductive layer and the second semiconductor member;
a second insulating member provided between the second conductive layer and the second charge storage member;
and
a second insulating layer including a third region and a fourth region, the third region being positioned between the second semiconductor member and the second charge storage member, the fourth region being positioned between the second region and the second semiconductor member,
wherein the first semiconductor member and the second semiconductor member are non-linear in the third direction.

9 more elements

A method for manufacturing a memory device comprising:

forming a first structural body and a second structural body, the first structural body extending along a first direction, the second structural body extending along the first direction, the second structural body being distant from the first structural body along a second direction crossing the first direction, the first structural body including a first film, the second structural body including a second film;
forming a third structural body including a first material insulating part, a second material insulating part and a third material insulating part, the first material insulating part being positioned between the first structural body and the second structural body in the second direction, the second material insulating part being positioned between the first material insulating part and the second structural body in the second direction, the third material insulating part being positioned between the first material insulating part and the second material insulating part, a third material of the third material insulating part being different from a first material of the first material insulating part and being different from a second material of the second material insulating part;
forming a first hole in the third structural body by removing a part of the first material insulating part, a part of the second material insulating part, and a part of the third material insulating part;
forming a fourth structural body having a second hole by forming a film of a fourth material in the first hole after recessing the first material insulating part and the second material insulating part exposed to the first hole;
forming a third hole by removing a part of the fourth structural body, a first residual portion and a second residual portion of the fourth structural body remaining in the third hole;
forming a fifth structural body from a fifth material by burying the fifth material in the third hole;
forming a fourth hole and a fifth hole by removing the first residual portion and the second residual portion after forming the fifth structural body;
and
forming a first functional film in the first film and the second film exposed to the fourth hole and the fifth hole, respectively,
wherein the first structural body and the second structural body member are non-linear in a third direction crossing a plane including the first direction and the second direction.

7 more elements

A method for manufacturing a memory device comprising:

forming a first structural body and a second structural body, the first structural body extending along a first direction, the second structural body extending along the first direction, the second structural body being distant from the first structural body along a second direction crossing the first direction, the first structural body including a first film, the second structural body including a second film,
forming a third structural body including a first material insulating part, a second material insulating part, and a third material insulating part, the first material insulating part being positioned between the first structural body and the second structural body in the second direction, the second material insulating part being positioned between the first material insulating part and the second structural body in the second direction, the third material insulating part being positioned between the first material insulating part and the second material insulating part, a third material of the third material insulating part being different from a first material of the first material insulating part and being different from a second material of the second material insulating part,
forming a first hole in the third structural body by removing a part of the first material insulating part, a part of the second material insulating part, and a part of the third material insulating part;
forming a fourth structural body having a second hole by forming a film of a fourth material in the first hole after selectively forming a spacer insulating part on the third material insulating part exposed to the first hole,
forming a third hole by removing a part of the fourth structural body, a first residual portion and a second residual portion of the fourth structural body remaining in the third hole;
forming a fifth structural body from a fifth material by burying the fifth material in the third hole;
forming a fourth hole and a fifth hole by removing the first residual portion and the second residual portion after forming the fifth structural body;
and
forming a first functional film in the first film and the second film exposed to the fourth hole and the fifth hole, respectively,
wherein the first structural body and the second structural body are non-linear in a third direction crossing a plane including the first direction and the second direction.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/917,954Filed 12 Mar 2018
Priority: JP 2017-16708831 Aug 2017
Published: US 2019/0067319 A128 Feb 2019
Granted: 11 Jun 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification31 codes

H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/10
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the top-view layout
H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35
Characterised by the memory core region: with a cell select transistor, e.g. NAND

Family

US 2019/0067319 A1Pre-grant publication · published 28 Feb 2019
US 10,319,740 B2This patent

From the US filing history. Foreign family members aren’t listed.

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