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US 10,319,736 B2Granted
Vertical memory structure with stress-inducing insulating layers
AssigneeSK hynix Inc.
InventorsJeong Seob Oh, Dong Hyoub Kim
Life of this patent
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Abstract
The present disclosure relates to a semiconductor device including a stress control insulating layer or a stress control pattern to control a stress applied to an interlayer insulating layer or a stacked body in a desirable direction.
Claims13
A semiconductor device, comprising:
- a first stacked body including at least one first sub-set, in which a first conductive pattern and a first insulating structure are stacked;
- a second stacked body arranged on the first stacked body and including at least one second sub-set, in which a second conductive pattern and a second insulating structure are stacked;
- and
- a channel layer penetrating the first stacked body and the second stacked body;
- wherein the first insulating structure induces a first stress and the second insulating structure induces a second stress in a direction opposite to the first stress,
- wherein the first insulating structure includes an upper first stress control insulating layer, a lower first stress control insulating layer, and a first interlayer insulating layer arranged between the upper first stress control insulating layer and the lower first stress control insulating layer,
- wherein the second insulating structure includes an upper second stress control insulating layer, a lower second stress control insulating layer, and a second interlayer insulating layer arranged between the upper second stress control insulating layer and the lower second stress control insulating layer,
- wherein the upper first stress control insulating layer and the lower first stress control insulating layer are formed of an oxide including a material having a different lattice constant from silicon constituting a lattice structure of the first interlayer insulating layer, and
- wherein the upper second stress control insulating layer and the lower second stress control insulating layer are formed of an oxide including a material having a different lattice constant from silicon constituting a lattice structure including the second interlayer insulating layer.
6 more elements
A semiconductor device, comprising:
- a channel layer;
- and
- insulating structures surrounding the channel layer and stacked to be spaced apart from one another,
- wherein each of the insulating structures includes:
- a first stress control insulating layer inducing a first stress;
- a second stress control insulating layer inducing a second stress in directions opposite to the first stress;
- and
- an interlayer insulating layer arranged between the first stress control insulating layer and the second stress control insulating layer,
- wherein the interlayer insulating layer includes a silicon oxide, and
- wherein one of the first stress control insulating layer and the second stress control insulating layer is formed of an oxide including a material having a smaller lattice constant than a silicon constituting a lattice structure of the silicon oxide, and the other is formed of an oxide including a material having a greater lattice constant than the silicon.
7 more elements
A semiconductor device, comprising:
- a first stacked body having a first end portion forming a first stair structure;
- a second stacked body arranged to be spaced apart from the first stacked body, wherein the second stacked body has a second end portion forming a second stair structure and the second end portion adjacent to the first end portion of the first stacked body;
- contact plugs contacting the first end portion and the second end portion;
- and
- a stress control insulating layer filling a space between the first end portion and the second end portion and penetrated by the contact plugs,
- wherein the stress control insulating layer includes:
- a first material layer arranged closer to the first stacked body than the second stacked body;
- and
- a second material layer arranged closer to the second stacked body than the first stacked body, and
- wherein the stress control insulating layer applies stress toward at least one of the first stacked body and the second stacked body.
7 more elements
Dependencies are inferred from the claim text.