Transistor element including a buried insulating layer having enhanced functionality

A transistor element, comprising:

• a channel region formed in a semiconductor layer and being laterally positioned between a drain region and a source region;
• a control gate electrode structure formed on said channel region;
• a buried insulating layer formed below said semiconductor layer and comprising a charge trapping material;
• and
• a semiconductor body region formed below said buried insulating layer and being connected for receiving a control voltage, wherein said semiconductor body region comprises first and second doped regions for adjusting a type of charge carriers to be trapped in said charge trapping layer, said second doped region is of inverse conductivity type compared to said first doped region, a first portion of said first doped region and a second portion of said second doped region directly contact said buried insulating layer, said first and second portions are disposed vertically below and overlapping said control gate electrode structure when viewed from above said control gate electrode structure, and said first portion is disposed vertically below and overlapping one of said source region or said drain region, and said second portion is disposed vertically below and overlapping the other of said source region or said drain region.

A transistor element, comprising:

• a channel region formed in a semiconductor layer and being laterally positioned between a drain region and a source region;
• a control gate electrode structure formed on said channel region;
• a buried insulating layer formed below said semiconductor layer and comprising a high-k dielectric material;
• and
• a semiconductor body region formed below said buried insulating layer and being connected for receiving a control voltage, wherein said semiconductor body region comprises first and second doped regions, said second doped region is of inverse conductivity type compared to said first doped region, a first portion of said first doped region and a second portion of said second doped region directly contact said buried insulating layer, said first and second portions are disposed vertically below and overlapping said control gate electrode structure when viewed from above said control gate electrode structure, and said first portion is disposed vertically below and overlapping one of said source region or said drain region, and said second portion is disposed vertically below and overlapping the other of said source region or said drain region.