US 10,319,721 B2Granted

Spacer for dual epi CMOS devices

AssigneeInternational Business Machines Corporation

InventorSoon-Cheon Seo

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Abstract

Aspects of the disclosure include a method for making a semiconductor, including patterning a first transistor having one or more gate stacks on a first source-drain area and second transistor comprising one or more gate stacks on a second source-drain area, forming dielectric spacers on gate stack side walls, depositing a first nitride liner on the first and second transistors. The method also includes masking the second transistor and etching to remove the first nitride material and the spacer from the first source-drain area and growing a first epitaxial layer on the first source-drain area by an epitaxial growth process. The method also includes depositing a second nitride liner on the first and second transistors. The method also includes masking the first transistor. The method also includes etching to remove the second nitride material from the second source-drain area and growing a second epitaxial layer on the second source-drain area by an epitaxial growth process.

A semiconductor device, comprising:

a first semiconductor structure having one or more first gate stacks on an upper surface of a first semiconductor fin that includes a first source-drain area having a horizontal surface on an upper surface of the first source-drain area;
a second semiconductor structure having one or more second gates stacks on an upper surface of a second semiconductor fin that includes a second source-drain area having a horizontal surface on an upper surface of the second source-drain area;
a first spacer on opposing sides of each first gate stack, the first spacer directly disposed on the upper surface of the first semiconductor fin and having a first spacer thickness;
a second spacer on opposing sides of each second gate stack, the second spacer directly disposed on the upper surface of the second semiconductor fin and having a second spacer thickness;
a first flat layer directly disposed on the upper surface of the first semiconductor fin, the first flat layer comprising at least one merged crystalline epitaxial layer disposed on opposing sides of the first source-drain area directly adjacent to a surface of the first spacer opposite the one or more first gate stacks, the first epitaxial layer extending the length of the first source-drain area and covering the horizontal surface of the first source-drain area except areas covered by the one or more first gate stacks;
and
a second flat layer directly disposed on the upper surface of the second semiconductor fin, the second flat layer comprising at least one merged crystalline epitaxial layer disposed on opposing sides of the second source-drain area directly adjacent to a surface of the second spacer opposite the one or more second gate stacks;
wherein the first spacer thickness is equal to the second spacer thickness, and
wherein a bottom surface of the first epitaxial layer extends below a bottom of the first gate stacks and a bottom surface of the second epitaxial layer extends below a bottom of the second gate stacks.

6 more elements

Facts

Application

15/166,560Filed 27 May 2016 · division

Priority

11 Dec 2015

Published

US 2017/0170179 A115 Jun 2017

Granted

11 Jun 2019

Term ends

Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10D 84/853
Complementary IGFETs, e.g. CMOS: comprising FinFETs
H10D 84/017
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their source or drain regions, e.g. silicided source or drain regions
H10D 84/0184
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their gate sidewall spacers
H10D 84/0193
The components including complementary IGFETs, e.g. CMOS devices: the components including FinFETs

Abstract

Claims4