Semiconductor device structure and manufacturing method thereof

A semiconductor device, comprising:

• a first reference voltage circuit including:
• a first transistor formed on a semiconductor substrate and comprising a first gate structure and a first drain terminal, the first gate structure comprising a first layer having a first conductive type;
• a second transistor formed on the semiconductor substrate and configured to include a threshold voltage level different than a threshold voltage of the first transistor, the second transistor comprising a second gate structure, a second drain terminal and a source terminal, the second gate structure comprising a second layer having the first conductive type;
• and
• a current source disposed between the source terminal and a ground terminal;
• and
• a second reference voltage circuit including:
• a third transistor comprising a third gate structure having a fourth layer;
• and
• a fourth transistor configured to include a threshold voltage level different than a threshold voltage of the third transistor, the fourth transistor including a fourth gate structure, the fourth gate structure comprising:
• a fifth layer;
• and
• a sixth layer disposed over the fifth layer, wherein
• each of the first gate structure and the second gate structure further comprises a metal layer, the metal layer of the first and second gate structures being formed between the semiconductor substrate and each of the first layer of the first transistor and the second layer of the second transistor,
• the second gate structure further comprises a third layer disposed between the metal layer of the second transistor and the second layer, the third layer being absent from the first gate structure,
• a first reference voltage level, defined as the difference between the threshold voltages of the first transistor and the second transistor, at a node between the source terminal and the current source is coupled to a first non-reference circuit in the semiconductor device, and
• the third transistor and the fourth transistor are coupled to provide a second reference voltage for a second non-reference circuit in the semiconductor device and the second reference voltage is different from the first reference voltage.