Semiconductor packages

A semiconductor package comprising:

• a substrate comprising a signal pattern on an upper surface thereof;
• a chip stack on the upper surface of the substrate;
• and
• a first semiconductor chip and one or more spacers that are between the substrate and the chip stack,
• wherein the first semiconductor chip and the one or more spacers are spaced apart from each other,
• wherein the chip stack comprises one or more second semiconductor chips stacked on the substrate, and a third semiconductor chip between the substrate and the chip stack,
• wherein the one or more spacers and the first semiconductor chip are adjacent to respective corners of a lowermost second semiconductor chip, in plan view, and
• wherein the one or more spacers have a same planar shape as the first semiconductor chip,
• wherein the third semiconductor chip is laterally spaced apart from the first semiconductor chip and the one or more spacers and is opposite to the first semiconductor chip,
• wherein the chip stack further comprises one or more fourth semiconductor chips on the one or more second semiconductor chips,
• wherein the one or more second semiconductor chips have a first offset stack structure of a first stepped shape tilted in a first direction, and
• wherein the one or more fourth semiconductor chips have a second offset stack structure of a second stepped shape tilted in a second direction that is opposite the first direction,
• wherein the signal pattern comprises a third signal pad spaced apart from the chip stack in the first direction and electrically connected to the third semiconductor chip, and a fourth signal pad spaced apart from the chip stack in the first direction and electrically connected to at least one of the fourth semiconductor chips, and
• wherein a third distance between the third signal pad and the fourth signal pad is less than a fourth distance between the fourth signal pad and a second side of the lowermost second semiconductor chip.