Stacked semiconductor architecture including semiconductor dies and thermal spreaders on a base die

A stacked semiconductor architecture for a semiconductor package, comprising:

• a base die;
• a plurality of stacked semiconductor dies on the base die;
• and
• a plurality of thermal spreaders on the base die, the plurality of thermal spreaders disposed on the base die in one or more gaps between the plurality of stacked semiconductor dies or in one or more areas on the base die that are adjacent to the plurality of stacked semiconductor dies, wherein at least one of the thermal spreaders is formed from a plurality of interleaved dielectric and metal layers.

A method of forming a stacked semiconductor architecture for a semiconductor package, comprising:

• disposing a plurality of stacked semiconductor dies on a base die;
• disposing a plurality of thermal spreaders on the base die, the plurality of thermal spreaders arranged on the base die in one or more gaps between the plurality of stacked semiconductor dies or in one or more areas on the base die that are adjacent to the plurality of stacked semiconductor dies;
• and
• electrically coupling the base die to the plurality of stacked semiconductor dies and the plurality of thermal spreaders.

A semiconductor package, comprising:

• a base die;
• a plurality of stacked semiconductor dies on the base die;
• a plurality of thermal spreaders on the base die, the plurality of thermal spreaders disposed in one or more gaps between the plurality of stacked semiconductor dies or in one or more areas on the base die that are adjacent to the plurality of stacked semiconductor dies;
• and
• electrical connections between two or more of the base die, the plurality of stacked semiconductor dies, and the plurality of thermal spreaders.