Back to results
US 10,319,696 B1Granted
Methods for fabricating 3D semiconductor device packages, resulting packages and systems incorporating such packages
AssigneeMicron Technology, Inc.
InventorEiichi Nakano
Life of this patent
Estimating the term…
Abstract
Methods of forming semiconductor device packages comprising stacking multiple dice, the die stack exhibiting thin bond lines and having an outer environmental coating, the bond lines and environmental coating comprising an in situ formed compound. Semiconductor device packages so formed and electronic systems incorporating such packages are also disclosed.
Claims18
A method for fabricating a semiconductor device package, the method comprising:
- adhering a wafer comprising laterally spaced semiconductor die locations thereof to a carrier substrate with an active surface of the wafer facing the carrier substrate;
- forming a dielectric material over a back side of the wafer;
- placing a first level of singulated semiconductor dice in mutually laterally spaced relationship over respective semiconductor die locations;
- connecting conductive pillars protruding from the back side of the wafer through the dielectric material to aligned terminal pads of the singulated semiconductor dice;
- and forming a dielectric material over back sides of the singulated semiconductor dice of the first level and into spaces therebetween.
2 more elements
A method of forming a semiconductor device package, the method comprising:
- stacking multiple levels of singulated semiconductor dice in mutually laterally spaced relationship over respective semiconductor die locations on a back side of a wafer;
- before stacking each singulated semiconductor die, forming a dielectric bond line material over a back side of a semiconductor die location or a back side of a lower level of singulated semiconductor die;
- connecting terminal pads of singulated dice to respective conductive pillars exposed through the dielectric bond line material over the back sides of the semiconductor die locations or over the back sides of the lower level of singulated semiconductor dice;
- making cuts of a first width into spaces between the singulated semiconductor dice, into a material in scribe areas thereof and into the material of the wafer within scribe areas between semiconductor die locations;
- forming a coating over back sides of uppermost dice of the stacks, over sides of the singulated semiconductor dice and over the material of the wafer between semiconductor die locations;
- and
- making cuts of a second, narrower width between the stacks into and through remaining material of the wafer between the semiconductor die locations.
4 more elements
Dependencies are inferred from the claim text.