Capping poly channel pillars in stacked circuits

A system comprising:

• a memory controller;
• and
• a three-dimensional stacked memory device coupled to the memory controller, the memory device including:
• a source conductor over a semiconductor substrate;
• an electrical isolation layer;
• multiple layers of cells vertically stacked adjacent each other between the source conductor proximate a cell closest to the semiconductor substrate, and the electrical isolation layer proximate a cell farthest from the semiconductor substrate;
• a conductive channel extending through the multiple layers of cells to the source conductor, the conductive channel to electrically couple the cells to the source conductor;
• and
• a conductive cap of metallic material selectively deposited on the conductive channel to completely cover the conductive channel proximate the electrical isolation layer with metallic growth isolated to the conductive channel and not in an area of the electrical isolation layer to form an isolated ohmic and an electrical contact with the conductive channel, wherein the conductive cap and the electrical isolation layer lacking polishing artifacts that result from chemical mechanical processing (CMP), wherein polishing artifacts include surface contamination or other imperfections in a crystalline structure of the electrical isolation layer proximate the conductive cap.