Conditions for burn-in of high power semiconductors
AssigneeTransphorm Inc.
InventorsKurt Vernon Smith, Likun Shen, David Michael Rhodes, Ronald Avrom Barr, James Leroy McKay
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AssigneeTransphorm Inc.
InventorsKurt Vernon Smith, Likun Shen, David Michael Rhodes, Ronald Avrom Barr, James Leroy McKay
Estimating the term…
Techniques for improving reliability of III-N devices include holding the III-N devices at a first temperature less than or equal to 30° for a first period of time while applying a first gate-source voltage lower than a threshold voltage of the III-N devices and a first drain-source voltage greater than 0.2 times a break down voltage of the III-N devices; and holding the III-N devices at a second temperature greater than the first temperature for a second period of time while applying a second gate-source voltage lower than a threshold voltage of the III-N devices and a second drain-source voltage greater than 0.2 times a breakdown voltage of the III-N devices. After holding the III-N devices at the first and second temperatures, screening the III-N devices based on electrical performance of one or more parameters of the III-N devices.
A method of testing a plurality of III-N devices each comprising a source, a gate, and a drain, the method comprising:
A method of assuring quality and reliability of a III-N device, the device including a package, a gate, a source, and a drain, the method comprising:
A method of testing a wafer including a plurality of III-N electronic devices each comprising a source, a gate, and a drain, the method comprising:
A system for testing a plurality of III-N devices, the system comprising:
A method of testing a plurality of III-N devices each comprising a source, a gate, and a drain, the method comprising:
Dependencies are inferred from the claim text.