CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture

A method of fabricating an integrated circuit structure, the method comprising:

• forming a first semiconductor device over a substrate, wherein forming the first semiconductor device comprises:
• forming a group IV semiconductor nanowire channel region;
• forming a first source region and a first drain region electrically coupled with the group IV semiconductor nanowire channel region;
• and
• forming a first gate stack comprising a gate insulator and a gate conductor coaxially wrapping completely around the group IV semiconductor nanowire channel region;
• and
• forming a second semiconductor device over the substrate, wherein forming the second semiconductor device comprises:
• forming a group III-V semiconductor nanowire channel region, wherein the group III-V semiconductor nanowire channel region is co-planar with the group IV semiconductor nanowire channel region;
• forming a second source region and a second drain region electrically coupled with the group III-V semiconductor nanowire channel region;
• and
• forming a second gate stack comprising a gate insulator and a gate conductor coaxially wrapping completely around the group III-V semiconductor nanowire channel region.