Parallel plate waveguide for power semiconductor package

A power semiconductor package, comprising:

• a substrate comprising a lowermost metal layer, an uppermost metal layer, and an intermediary metal layer separated from the lowermost metal layer by a first insulating layer and separated from the uppermost metal layer by a second insulating layer, the uppermost metal layer being patterned into a plurality of strips which extend in parallel over a width of the substrate;
• a first group of semiconductor dies attached to a first one of the strips of the uppermost metal layer and evenly distributed over the width of the first strip, each semiconductor die in the first group having an insulated or isolated face attached to the first strip;
• a second group of semiconductor dies attached to the first strip of the uppermost metal layer and evenly distributed over the width of the first strip, each semiconductor die in the second group having an insulated or isolated face attached to the first strip;
• a third group of semiconductor dies attached to a second one of the strips of the uppermost metal layer and evenly distributed over the width of the second strip, each semiconductor die in the third group having an insulated or isolated face attached to the second strip;
• and
• a fourth group of semiconductor dies attached to the second strip of the uppermost metal layer and evenly distributed over the width of the second strip, each semiconductor die in the fourth group having an insulated or isolated face attached to the second strip,
• wherein the first group of semiconductor dies is electrically connected in series to the second group of semiconductor dies,
• wherein the third group of semiconductor dies is electrically connected in series to the fourth group of semiconductor dies.