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US 10,319,630 B2Granted
Encapsulated damascene interconnect structure for integrated circuits
AssigneesSTMicroelectronics S.r.l., International Business Machines Corporation
InventorsJohn H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu
Life of this patent
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Abstract
A plurality of metal tracks are formed in a plurality of intermetal dielectric layers stacked in an integrated circuit die. Thin protective dielectric layers are formed around the metal tracks. The protective dielectric layers act as a hard mask to define contact vias between metal tracks in the intermetal dielectric layers.
Claims19
A device comprising:
- a semiconductor substrate;
- a plurality of transistors in the semiconductor substrate;
- a first intermetal dielectric layer overlying the semiconductor substrate;
- a plurality of first metal tracks overlying the first intermetal dielectric layer;
- a first protective dielectric layer encapsulating each of the first metal tracks on at least three sides;
- a second intermetal dielectric layer overlying the first metal tracks and the first protective dielectric layer;
- a plurality of second metal tracks overlying the second intermetal dielectric layer;
- a second protective dielectric layer encapsulating each of the second metal tracks on at least three sides, the first and second intermetal dielectric layers being selectively etchable with respect to the first and second protective dielectric layers;
- and
- a plurality of L-shaped unitary vias extending between selected ones of the first and second metal tracks, each L-shaped unitary via having a first section of a first substantially uniform width directly below a second section of a second, different, substantially uniform width.
7 more elements
A device comprising:
- a semiconductor substrate;
- a first intermetal dielectric layer overlying the semiconductor substrate;
- a first metal track overlying the first intermetal dielectric layer;
- a first protective dielectric layer encapsulating the first metal track on at least three sides;
- a second intermetal dielectric layer overlying the first metal track and the first protective dielectric layer;
- a second metal track on the second intermetal dielectric layer;
- a second protective dielectric layer encapsulating the second metal track on at least three sides;
- and
- a unitary via in the first and second intermetal dielectric layers, the unitary via having a first section of a first substantially uniform width directly below a second section of a second, different, substantially uniform width.
6 more elements
A device comprising:
- a semiconductor substrate;
- a plurality of transistors in the semiconductor substrate;
- a first intermetal dielectric layer overlying the semiconductor substrate;
- a plurality of first metal tracks overlying the first intermetal dielectric layer;
- a first protective dielectric layer encapsulating each of the first metal tracks on at least three sides;
- a second intermetal dielectric layer overlying the first metal tracks and the first protective dielectric layer;
- a plurality of second metal tracks overlying the second intermetal dielectric layer;
- a second protective dielectric layer encapsulating each of the second metal tracks on at least three sides, the first and second intermetal dielectric layers being selectively etchable with respect to the first and second protective dielectric layers;
- a plurality of unitary vias coupling selected ones of the first and second metal tracks, the unitary vias having sections of different widths, the first protective dielectric layer forming at least one sidewall that determines a first width of the unitary via;
- a first conductive plug in the unitary via, the first conductive plug being integral with the at least one of the second metal tracks;
- a third intermetal dielectric layer overlying the second intermetal dielectric layer;
- a plurality of third metal tracks overlying the third intermetal dielectric layer;
- a third protective dielectric layer encapsulating each of the third metal tracks on at least three sides;
- a fourth intermetal dielectric layer overlying the plurality of third metal tracks and the third protective dielectric layer;
- a plurality of fourth metal tracks overlying the fourth intermetal dielectric layer;
- a fourth protective dielectric layer encapsulating each of the fourth metal tracks on at least three sides;
- and
- a unitary via in the third and fourth intermetal dielectric layers exposing the first conductive plug.
15 more elements
A device, comprising:
- a substrate;
- a first metal track on the substrate;
- a second metal track on the substrate, the second metal track being spaced apart from the first metal track;
- a dielectric layer having a first portion and a second portion, the first portion of the dielectric layer completely surrounding four sides of the first metal track, the second portion of the dielectric layer being on the second metal track and having an opening in which the second portion of the dielectric layer is not on a part of a surface of the second metal track;
- and
- a unitary via having a vertical narrow portion extending between the first metal track and the second metal track and a horizontal wide portion that couples to the vertical narrow portion, the horizontal wide portion of the unitary via being positioned in the opening and being physically and electrically coupled to the part of the surface of the second metal track.
3 more elements
Dependencies are inferred from the claim text.