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US 10,319,629 B1Granted
Skip via for metal interconnects
AssigneeInternational Business Machines Corporation
InventorsChih-Chao Yang, Lawrence A. Clevenger, Brent A. Anderson, Nicholas A. Lanzillo
Life of this patent
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Abstract
Semiconductor devices including skip via structures and methods of forming the skip via structure include interconnection between two interconnect levels that are separated by at least one other interconnect level, i.e., skip via to connect Mx and Mx+2 interconnect levels, wherein a portion of the intervening metallization level (MX+1) is in a pathway of the skip via.
Claims20
A method of forming a skip-via structure in a semiconductor device, the method comprising:
- forming a first interconnect level (Mx) comprising depositing a first dielectric layer on a substrate including one or more semiconductor devices, forming at least one first metal conductor in the first dielectric layer, wherein the at least one metal conductor and the first dielectric have coplanar surfaces, and depositing a first cap layer on the coplanar surfaces;
- forming a second interconnect level (Mx+1) comprising depositing a second dielectric layer on the first cap layer, forming at least one second metal conductor in the second dielectric layer, wherein the second metal conductor comprises a second cap layer on a top surface thereof and a liner layer that collectively encapsulate the second metal conductor;
- forming a third interconnect level (Mx+2) comprising depositing a third dielectric layer on the second interconnect level;
- forming a via opening in the second and third dielectric layers to the first metal conductor, wherein the via opening exposes a portion of the second cap layer, a sidewall of the second metal conductor, and a portion of the first cap layer;
- removing the first cap layer at a bottom of the via opening to expose a surface of the first metal conductor;
- depositing a spacer layer on sidewalls of the via opening including the sidewall of the second metal conductor;
- and
- filling the via opening with a metal conductor, wherein the second metal conductor in the second interconnect level is electrically isolated from the filled via opening extending from the third interconnect level to the first metal conductor of the first interconnect level, and wherein the first and second cap layers have different etch selectivities.
5 more elements
A semiconductor device comprising:
- a first interconnect level (Mx) comprising a first dielectric layer, a first metal conductor, and a first capping layer overlaying the first metal conductor;
- a second interconnect level (Mx+1) on the first interconnect layer comprising a second dielectric layer, a second metal conductor, and a second capping layer overlaying the second metal conductor, wherein the second capping layer has a different etch selectivity relative to the first capping layer;
- a third interconnect level (Mx+2) on the second interconnect level comprising a third dielectric layer, and a third metal conductor;
- and
- a skip via opening filled with a metal extending from the third interconnect level to the first interconnect level, wherein a portion of the second metal conductor including a sidewall thereof in the second interconnect level is in a path of the skip via opening and is electrically isolated from the filled metal via opening.
2 more elements
A semiconductor device comprising:
- a first interconnect level (Mx) comprising a first dielectric layer, a first metal conductor, and a first capping layer overlaying the first metal conductor and a first liner layer encapsulating the first metal conductor;
- a second interconnect level (Mx+1) on the first interconnect layer comprising a second dielectric layer, a second metal conductor, and a second capping layer overlaying the second metal conductor and a second liner layer encapsulating the second metal conductor, wherein the second capping layer has a different etch selectivity relative to the first capping layer;
- a third interconnect level (Mx+2) on the second interconnect level comprising a third dielectric layer, and a third metal conductor;
- and
- a skip via including a metal extending from the third interconnect level to the first interconnect level, wherein a portion of the second metal conductor including the second capping layer and a sidewall thereof in the second interconnect level is in a path of the skip via during formation thereof, wherein the sidewall comprises a self-formed barrier layer effective in combination with the capping layer to be electrically isolated from the skip via.
2 more elements
Dependencies are inferred from the claim text.