Cut metal gate process for reducing transistor spacing

A method comprising:

• providing a structure having:
• a substrate;
• a first fin, a second fin, and a third fin over the substrate and oriented lengthwise generally along a first direction;
• metal gate structures over the first, the second, and the third fins and oriented lengthwise generally along a second direction perpendicular to the first direction, wherein each gate structure includes a high-k dielectric layer and a metal gate electrode;
• first and second epitaxial semiconductor source/drain (S/D) features over the first and the second fins respectively, wherein the first and the second epitaxial semiconductor S/D features merge along the second direction;
• and
• a first dielectric layer over the substrate, the first, the second, and the third fins, and the first and the second epitaxial semiconductor S/D features, the first dielectric layer filling space between the metal gate structures;
• performing a first etching process to a first area between the first and the second fins and to a second area between the second and the third fins, wherein the first etching process is tuned to selectively etch the first and the second epitaxial semiconductor S/D features and the first dielectric layer but not the metal gate structures;
• performing a second etching process to the second area, wherein the second etching process is tuned to selectively etch the metal gate structures to form a trench in the metal gate structures;
• and
• forming a second dielectric layer in the trench.

A semiconductor structure, comprising:

• a substrate;
• first and second fins over the substrate and oriented lengthwise generally along a first direction, wherein bottom portions of the first and the second fins are separated by an isolation feature;
• first and second epitaxial semiconductor source/drain (S/D) features over the first and second fins, respectively;
• and
• a first dielectric layer disposed between and in physical contact with the first and the second epitaxial semiconductor S/D features, wherein the first dielectric layer is defined by a first interface between the first dielectric layer and the first epitaxial semiconductor S/D feature, and a second interface between the first dielectric layer and the second epitaxial semiconductor S/D feature, and wherein a bottom surface of the first dielectric layer is disposed below a top surface of the isolation feature.