Semiconductor device and semiconductor system

A semiconductor device comprising:

• an operation control circuit configured for generating a first signal based on a level of a core voltage being lower than a level of a reference voltage;
• and
• an error correction circuit configured for correcting an error of read data according to a read parity and generating output data based on the first signal;
• and
• a memory array configured to output the read data and the read parity to the error correction circuit based on a read operation,
• wherein the operation control circuit is configured to generate a second signal based on the level of the core voltage being lower than a level obtained by subtracting a level of a predetermined voltage from the level of the reference voltage,
• wherein the operation control circuit comprises a voltage detection circuit, and
• wherein the voltage detection circuit generates the first detection signal which is enabled, based on the level of the core voltage being equal to or higher than the level of the reference voltage, generates the second detection signal which is enabled, based on the level of the core voltage being lower than the level of the reference voltage and being equal to or higher than the level obtained by subtracting the level of the predetermined voltage from the level of the reference voltage, and generates the third detection signal which is enabled, based on the level of the core voltage being lower than the level obtained by subtracting the level of the predetermined voltage from the level of the reference voltage.

A semiconductor system comprising:

• a first semiconductor device configured for outputting a command and being inputted with output data;
• and
• a second semiconductor device configured for generating a first signal and a second signal depending upon an internal temperature or a level of a core voltage, and generating the output data by correcting an error of read data according to a read parity based on the first signal, based on a read operation being performed based on the command,
• wherein the read parity and the read data are outputted from a memory array, included in the second semiconductor device, in the read operation,
• wherein the second semiconductor device is configured to generate the first signal based on the internal temperature being equal to or higher than a first predetermined temperature and to generate the second signal based on the internal temperature being equal to or higher than a second predetermined temperature,
• wherein the first predetermined temperature is different from the second predetermined temperature,
• wherein the second semiconductor device comprises a temperature sensor, and
• wherein the temperature sensor generates the first detection signal which is enabled, based on the internal temperature being lower than the first predetermined temperature, generates the second detection signal which is enabled, based on the internal temperature being equal to or higher than the first predetermined temperature and being lower than the second predetermined temperature, and generates the third detection signal which is enabled, based on the internal temperature being equal to or higher than the second predetermined temperature.

A semiconductor device comprising:

• an operation control circuit configured to generate a first to third detection signals based on an internal temperature of the semiconductor device;
• and
• an error correction circuit configured to output read data as output data with or without performing an error correction operation and with or without performing a scrub operation based on the first to third detection signals,
• wherein the operation control circuit is configured to generate the second detection signal based on the internal temperature being equal to or higher than a first predetermined temperature and to generate the third detection signal based on the internal temperature being equal to or higher than a second predetermined temperature, and
• wherein the first predetermined temperature is different from the second predetermined temperature.

A semiconductor device comprising:

• an operation control circuit configured to generate a first to third detection signals based on a level of a core voltage of the semiconductor device;
• and
• an error correction circuit configured to output read data as output data with or without performing an error correction operation and with or without performing a scrub operation based on the first to third detection signals,
• wherein the operation control circuit is configured to generate the second detection signal based on a level of a core voltage being lower than a level of a reference voltage and to generate the third detection signal based on the level of the core voltage being lower than a level obtained by subtracting a level of a predetermined voltage from the level of the reference voltage.