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AssigneeCadence Design Systems, Inc.
InventorsSteven Lee Gregor, Puneet Arora, Norman Robert Card
Estimating the term…
An exemplary memory arrangement can be provided, which can include, for example, a memory(ies), and an algorithmic memory unit(s) (AMU) coupled to the memory(ies), wherein the AMU includes a programmed testplan algorithm(s) configured to test the memory(ies). The AMU(s) can further include a hardwired testplan(s) configured to test the memory(ies). A Joint Test Action Group (“JTAG”) controller may be coupled to the AMU(s), which can be configured to access logic of the programmed testplan algorithm(s). A direct access controller (DAC) can be coupled to the AMU(s), which can be configured to access internal nodes in the AMU(s). The DAC can be configured to activate the programmed testplan algorithm(s) using a minimally direct access pin interface in the AMU(s).
A memory apparatus, comprising:
A non-transitory computer-accessible medium having stored thereon computer-executable instructions for modifying at least one algorithmic memory unit (AMU), wherein, when a computer apparatus executes the instructions, the computer apparatus is configured to perform procedures comprising:
A method for modifying at least one algorithmic memory unit (AMU), comprising:
Dependencies are inferred from the claim text.