Apparatus and method for measuring performance of memory array
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChi-Hsu Chiu, Shih-Feng Huang, Yi-Sin Wang, Arjit Ashok
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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChi-Hsu Chiu, Shih-Feng Huang, Yi-Sin Wang, Arjit Ashok
Estimating the term…
The disclosure is related a method for testing and measuring the performances of electrical components on a semiconductor IC device through a test apparatus (also referred to as a testline) disposed in a scribe line between the semiconductor IC devices on a wafer. The test apparatus may include a built-in self-test (BIST) circuit and a duplication of the electrical components subjected to the performance measurement. Minimum and maximum testing voltages are provided to the test apparatus, where the range of voltage between the minimum and maximum testing voltages are divided into a plurality of testing operational voltages which are applied to the test apparatus. For each testing operational voltages, a memory array operation test is performed, where at least one of the testing operational voltages resulting in a performance failure is identified as the minimal operating voltage of the memory array.
A method for detecting minimal operation voltage of memory array, comprising:
A method of measuring an operation of a memory array, comprising:
A test apparatus, disposed in a scribe line of wafer, comprising:
Dependencies are inferred from the claim text.