Board level leakage testing for memory interface

A non-transitory computer-readable storage medium having stored thereon data representing sequences of instructions that, when executed by a processor, cause the processor to perform operations comprising:

• performing a test sequence for each logic cell of a plurality of logic cells for a memory interface, the test sequence including the following:
• setting a logical value of ‘1’ or ‘0’ for the logic cell,
• setting a high impedance for one or more other logic cells of the plurality of logic cells,
• generating a cell value of each logic cell of the plurality of logic cells based on a comparison of a signal value with a reference voltage,
• capturing the cell value, and
• shifting the cell value to a next logic cell;
• and
• identifying any shorted connections or open connections for the memory interface based at least in part on results of the test sequence for each of the plurality of logic cells.

A system comprising:

• a processor for processing of data;
• a memory for storage of data;
• a memory interface for the memory;
• and
• a plurality of logic cells for testing of the memory interface, each logic cell of the plurality of logic cells being connected to an interconnect for a respective memory element, wherein each logic cell of the plurality of logic cells includes:
• a driver to drive a signal onto the interconnect with the respective memory element,
• an element to generate a value for the logic cell by comparing a signal with a reference voltage,
• a flip-flop to capture a cell value for the logic cell, and
• a drive control element to control the value driven on the interconnect by the driver;
• wherein the processor is to identify failure conditions based at least in part on testing using the plurality of logic cells.