Semiconductor memory device

A semiconductor memory device comprising:

• a first memory cell which is capable of being set to any one of at least eight threshold voltages;
• a first bit line connected to the first memory cell;
• a word line connected to a gate of the first memory cell;
• and
• a sense amplifier connected to the first bit line,
• wherein a verification operation for verifying the threshold voltage of the first memory cell is performed after a programming operation is performed on the first memory cell,
• wherein the verification operation includes seven verification operations including
• a first verification operation in which a first voltage is applied to the word line,
• a second verification operation in which a second voltage higher than the first voltage is applied to the word line,
• a third verification operation in which a third voltage higher than the second voltage is applied to the word line,
• a fourth verification operation in which a fourth voltage higher than the third voltage is applied to the word line,
• a fifth verification operation in which a fifth voltage higher than the fourth voltage is applied to the word line,
• a sixth verification operation in which a sixth voltage higher than the fifth voltage is applied to the word line, and
• a seventh verification operation in which a seventh voltage higher than the sixth voltage is applied to the word line, and
• wherein the sense amplifier
• applies a charging voltage to the first bit line during two of the seven verification operations, and
• does not apply the charging voltage to the first bit line during the remaining five of the seven verification operations.