Circuits and methods of reference-current generation for flash

A reference-current generation circuit for flash, wherein the flash comprises at least two flash arrays, namely, a first memory array and a second memory array, consisting of memory cells arranged into rows and columns and having the same number of rows thereof;

• the reference-current generation circuit comprising a first row of reference cells and a second row of reference cells, and the first row of reference cells and the second row of reference cells are arranged by reference cells, with the first row of reference cells parallel with the other rows of the first memory array and having the same number of columns as the other rows thereof, and with a second row of reference cells parallel with the other rows of the second memory array and having the same number of columns as the other rows thereof;
• a word-line switching circuit is arranged between the first memory array and the second memory array and is extended between the first row of reference cells and the second row of reference cells, and under a Read operation mode of the flash, the word-line switching circuit causes the word lines of various rows of the first memory array to be disconnected with the word lines of various rows of the second memory array, and causes a first reference word line of the first row of reference cells to be disconnected with a second reference word line of the second row of reference cells;
• the first row of reference cells after programming enables various bit lines of the first memory array to form a first reference current, and the second row of reference cells after programming enables various bit lines of the second memory array to form a second reference current;
• and
• the first reference current is to be used as the reference current while performing a Read operation for the second memory array, and the second reference current is to be used as the reference current while performing a Read operation for the first memory array.