Semiconductor memory device
AssigneeSK hynix Inc.
InventorWon Sun Park
Life of this patent
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Abstract
Provided herein is a semiconductor memory device. The semiconductor memory device includes: a memory cell array including a plurality of memory blocks; a voltage generation circuit configured to generate a plurality of operating voltages; a decoder circuit configured to transmit the plurality of operating voltages to the memory cell array in response to a serial data signal that is sequentially inputted; and a control logic configured to generate the data signal, internal address signals and an internal clock signal in response to a command.
Claims20
A semiconductor memory device comprising:
- a memory cell array including a plurality of memory cells;
- a voltage generation circuit configured to generate a plurality of operating voltages;
- a decoder circuit configured to transmit the plurality of operating voltages to the memory cell array in response to a serial data signal that is sequentially inputted;
- and
- a control logic configured to generate the data signal, parallel internal address signals and an internal clock signal in response to a command.
The semiconductor memory device according to claim, wherein the control logic comprises:
- a microcontroller configured to selectively output a plurality of operation phase codes according to sub-operations forming the operation in response to the command;
- an encoding signal generation circuit configured to generate parallel N-bit encoding signals in response to the plurality of operation phase codes;
- and
- a sequential output circuit configured to convert the N-bit encoding signals into the data signal.
The semiconductor memory device according to claim
- wherein the register circuit comprises an “N” number of registers, and
- wherein each of the “N” number of registers is configured to output corresponding one of the internal data signals in response to corresponding one among the “N” number of clock signals.
A semiconductor memory device comprising:
- a control logic configured to generate parallel N-bit (N is a natural number) encoding signals according to an operation phase code, and to convert the N-bit encoding signals into a serial 1-bit data signal that is serially outputted;
- and
- a decoder circuit configured to restore the N-bit encoding signals from the 1-bit data signal, and then switch a plurality of operating voltages according to the restored N-bit encoding signals.
A semiconductor memory device comprising:
- a memory cell array;
- a voltage generation circuit configured to generate a plurality of operating voltages;
- a control logic configured to generate parallel N-bit encoding signals and parallel-to-serial convert the N-bit encoding signals into a serial 1-bit data signal toggling N times to represent the N-bit encoding signals;
- and
- a decoder circuit configured to transfer one or more of the operating voltages to the memory cell ay in response to the 1-bit data signal.
Dependencies are inferred from the claim text.