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US 10,319,443 B2Granted
Memory device and method of operating the same
AssigneeSK hynix Inc.
InventorHee Youl Lee
Life of this patent
Estimating the term…
Abstract
A memory device with a plurality of memory block may include a plurality of memory cells constituting a memory blocks, and two or more select transistors coupled to the plurality of memory cells constituting the memory block and configured to select the memory block, the two or more select transistors having different threshold voltages from one another.
Claims10
A memory device, comprising:
- a first cell string coupled to or isolated from a first bit line by first select transistors having different threshold voltages and coupled to or isolated from a first common source line by second select transistors having different threshold voltages;
- a second cell string coupled to or isolated from a second bit line by third select transistors having different threshold voltages and coupled to or isolated from the first common source line by fourth select transistors having different threshold voltages;
- a third cell string stacked on the first cell string, the third cell string being coupled to or isolated from the first bit line by fifth select transistors having different threshold voltages and coupled to or isolated from a second common source line by sixth select transistors having different threshold voltages;
- and
- a fourth cell string stacked on the second cell string, the fourth cell string being coupled to or isolated from the second bit line by seventh select transistors having different threshold voltages and coupled to or isolated from the second common source line by eighth select transistors having different threshold voltages,
- wherein different voltages are applied to the first common source line and the second common source line, respectively.
3 more elements
A method of operating a memory device, comprising:
- programming first and second select transistors so that the first and second select transistors have different threshold voltages, wherein the first select transistors are included in a first memory block and the second select transistors are included in a second memory block stacked on the first memory block;
- and
- selecting the first memory block by turning on all of the first select transistors and by turning off part of the second select transistors, or selecting the second memory block by turning on all of the second select transistors and by turning off part of the first select transistors,
- wherein the first memory block and the second memory block are coupled to different common source lines to which different voltages are applied, respectively.
1 more element
Dependencies are inferred from the claim text.