Write assist for a memory device and methods of forming the same

A write assist circuit for a semiconductor memory device, comprising:

• a core voltage bus configured to provide power to memory cells within the semiconductor memory device;
• a first pair of transistors coupled between a pull-up voltage and the core voltage bus;
• a second pair of transistors coupled between a pull-down voltage and the core voltage bus, the second pair of transistors each having a gate terminal that receives an enable signal that causes the second pair of transistors to connect the core voltage bus to the pull-down voltage during write operations to the memory cells,
• the write assist circuit and the memory cells having a common semiconductor layout that includes a repeating pattern of gate regions and active regions, wherein the write assist circuit utilizes a layout footprint of the common semiconductor layout that is equivalent to a footprint for three adjacent memory cells.

A method of controlling a semiconductor memory device that includes an array of memory cells arranged in a plurality of rows and columns and one or more write assist circuits within each column of the array of memory cells, the method comprising:

• providing a core voltage to memory cells within a column of the array of memory cells;
• and
• during a write operation, causing the one or more write assist circuits in the column to reduce the core voltage,
• wherein the one or more write assist circuits and the memory cells have a common static random access memory (SRAM) semiconductor layout that includes a repeating pattern of gate regions and active regions, and
• wherein the each of the one or more write assist circuits utilizes a layout footprint of the common SRAM semiconductor layout that is equivalent to a footprint for three adjacent memory cells with the column of the array of memory cells.