Static random access memory cell capable of performing differential operation

A method of controlling an SRAM cell, the SRAM cell comprising a data node portion comprising four transistors constituting first and second data nodes;

• a data controller comprising first and second pass-gate transistors configured to control read and write of data in the first and second data nodes;
• and a control transistor connected to the data node portion through the second data node and configured to be controlled based on a driving voltage of a second word line having an opposite polarity to a first word line transmitting a driving voltage to the data controller,
• wherein the data node portion comprises first and second pull-up transistors and first and second pull-down transistors,
• wherein a drain terminal of the control transistor is connected to a gate terminal of the first pull-up transistor, a gate terminal of the first pull-down transistor, and a source terminal of the second pull-up transistor through the second data node,
• a source terminal of the control transistor is connected to a source terminal of the second pass-gate transistor and a drain terminal of the second pull-down transistor through a third data node, and
• a gate terminal of the control transistor is connected to the second word line,
• wherein gate terminals of the first and second pass-gate transistors are connected to the first word line,
• a drain terminal of the first pass-gate transistor is connected to a first Bit Line (BL),
• a drain terminal of the second pass-gate transistor is connected to a second BL, and
• wherein a word line driver switches a driving voltage transmitted to the second word line from a negative value to a positive value when at least one of a charge from the first BL and a charge from the second BL is discharged for a predetermined time.