US 10,319,433 B2 · Memory devices and methods of operating the same

Abstract

A memory device includes a memory cell, a word line connected to the memory cell, a bit line connected to the memory cell, a complementary bit line connected to the memory cell, an auxiliary bit line, an auxiliary complementary bit line, and a switch circuit. The memory cell stores a single bit. The switch circuit electrically connects one of the bit line and the complementary bit line to one of the auxiliary bit line and the auxiliary complementary bit line, in response to a logic level of a data bit to be written in the memory cell during a write operation, by using at least one or more transistors of at least one dummy cell as a switch, and the at least one dummy cell does not store a data bit.

Claims20

Dependent claims

A memory device, comprising:

a memory cell configured to store a single bit;
a word line connected to the memory cell;
a bit line connected to the memory cell;
a complementary bit line connected to the memory cell;
an auxiliary bit line;
an auxiliary complementary bit line;
and
a switch circuit, wherein the switch circuit is configured to electrically connect one of the bit line and the complementary bit line to one of the auxiliary bit line and the auxiliary complementary bit line, in response to a logic level of a data bit to be written in the memory cell during a write operation, by using at least one or more transistors of at least one dummy cell as a switch, and the at least one dummy cell does not store a data bit.

5 more elements

A memory device comprising:

a memory cell array including a plurality of memory cells connected to a plurality of word lines, a plurality of bit lines, and a plurality of complementary bit lines, wherein the plurality of word lines extend in a first direction, the plurality of bit lines extend in a second direction crossing the first direction, and the plurality of complementary bit lines extend in the second direction;
a plurality of auxiliary bit lines extending in the second direction;
a plurality of auxiliary complementary bit lines extending in the second direction;
and
a switch circuit, wherein the switch circuit electrically connects one of a corresponding one of the bit lines and a corresponding one of the complementary bit lines to one of a corresponding one of the auxiliary bit lines and a corresponding one of the auxiliary complementary bit lines, in response to a logic level of a data bit to be written through each of the bit lines and each of the complementary bit lines in the memory cells during a write operation, by using at least one or more transistors of each of dummy cells as a switch, and each of the dummy cells does not store a data bit.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

15/915,660Filed 8 Mar 2018

Priority

KR 10-2017-010640723 Aug 2017

Published

US 2019/0066773 A128 Feb 2019

Granted

11 Jun 2019

Term ends

Not estimatedThe source records don’t support an estimate.

Classification9 codes

G11C 11/419
For memory cells of the field-effect type: read-write [R-W] circuits
G11C 7/12
Arrangements for writing information into, or reading information out from, a digital store: bit line control circuits, e.g. drivers, boosters,…
G11C 7/14
Arrangements for writing information into, or reading information out from, a digital store: dummy cell management; Sense reference voltage generators
G11C 7/18
Arrangements for writing information into, or reading information out from, a digital store: bit line organisation; Bit line lay-out

Memory devices and methods of operating the same

Life of this patent

Memory devices and methods of operating the same

Life of this patent

Abstract

Claims20