Circuits for pulse-width control in memory devices and related methods

A method for controlling a memory, the method comprising:

• with a drive circuit, receiving an input pulse and generating an output signal in response to receiving the input pulse;
• providing the output signal, through an output signal line, to first and second sense amplifiers of a plurality of sense amplifiers, the first sense amplifier being configured to control operations of a first memory cell of the memory and the second sense amplifier being configured to control operations of a second memory cell of the memory;
• and
• feeding the output signal back to the drive circuit as a feedback signal after the output signal has passed through the output signal line,
• wherein the output signal has a timing that depends on a timing of the feedback signal.

A control circuit for a plurality of sense amplifiers of a memory, the control circuit comprising:

• a drive circuit;
• an output signal line coupled to first and second sense amplifiers of the plurality of sense amplifiers, the output signal line having a first end coupled to the drive circuit and a second end, the first sense amplifier being coupled to a first memory cell of the memory and the second sense amplifier being coupled to a second memory cell of the memory;
• and
• a feedback line coupled to the second end of the output signal line and to the drive circuit.