Tunable negative bit line write assist and boost attenuation circuit

A method, comprising:

• forming a memory array comprising a plurality of static random access memory (SRAM) cells;
• forming a plurality of true bit lines each connected to a column of the memory array;
• forming a plurality of complement bit lines each forming a differential pair with, and in a same column as, one of the plurality of true bit lines;
• forming a write driver connected to each of the differential pair of bit lines in each of the plurality of SRAM cells of the memory array, the write driver comprising:
• a negative boost node;
• a discharge device coupled to ground and the negative boost node, the discharge device configured to receive a control signal and pull one of the plurality of true bit lines or one of the plurality of complement bit lines to ground in an active phase of a write cycle;
• and
• a boost capacitor coupled to the negative boost node, the boost capacitor configured to boost the one of the plurality of true bit lines or the one of the plurality of complement bit lines below ground;
• and
• forming a write assist attenuation circuit connected to the discharge device, the write assist attenuation circuit comprising a clamping device comprising an inverter, a first NFET, a second NFET, and a third NFET, each having a source-drain path connected to an output of the inverter which supplies the control signal to the source-drain paths of the first NFET, second NFET and third NFET, respectively, the clamping device being configured to modify the control signal as a function of supply voltage and process to attenuate an amount of the boost, and each of the first NFET, the second NFET, and the third NFET being connected to a first attenuation signal, a second attenuation signal, and a third attenuation signal, respectively,
• wherein the source-drain paths of the first NFET, the second NFET and the third NFET are connected in parallel with one another between the supply voltage and the output of the inverter with the source of each of the first NFET, the second NFET and the third NFET being connected directly to the output of the inverter.