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US 10,319,429 B2Granted
SRAM with error correction in retention mode
AssigneeAmbiq Micro, Inc.
InventorsChristophe J. Chevallier, Stephen James Sheafor
Life of this patent
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Abstract
A method for storing information in SRAM bit cell arrays provides for lowering voltage supplied to the SRAM bit cell arrays, with voltage lowering controlled by a connected voltage control circuit. Writing, reading, and correcting information storable in the SRAM bit cell arrays is accomplished using an error correcting code (ECC) block connected to at least some of the SRAM bit cell arrays. The ECC block is configurable to repair stored information.
Claims20
An apparatus comprising:
- a SRAM array with an adjustable power supply and peripheral circuitry;
- a register connected to peripheral circuitry to store a retention voltage value for the adjustable power supply, wherein the peripheral circuitry has an ECC circuit to detect at least one error in a SRAM word;
- and
- wherein the retention voltage value is set to a level ensuring loss of at least some SRAM bits in SRAM words retained in the SRAM array.
1 more element
A method comprising:
- writing data to a SRAM array, the data including error correction code (ECC) data with the voltage powering the SRAM array being an operation voltage;
- lowering the voltage powering the SRAM array to a retention voltage that is lower than the operation voltage and at least some SRAM bits in the SRAM array are lost;
- and
- raising the voltage powering the SRAM array to the operation voltage and repairing the data using the ECC data.
1 more element
Dependencies are inferred from the claim text.