Offset-cancellation sensing circuit (OCSC)-based non-volatile (NV) memory circuits

A sensing circuit, comprising:

• a means for pre-charging a gate of a differential transistor to a pre-charge voltage based on a supply voltage coupled to a supply node, the differential transistor coupled between a non-volatile (NV) memory circuit and a ground node, and a means for pre-charging a gate of a complement differential transistor to a complement pre-charge voltage based on the supply voltage coupled to the supply node, the complement differential transistor coupled between a complement NV memory circuit and the ground node;
• a means for pre-charging a capacitor circuit coupled between the gate of the differential transistor and the ground node based on the pre-charge voltage applied to the gate of the differential transistor, and a means for pre-charging a complement capacitor circuit coupled between the gate of the complement differential transistor and the ground node based on the complement pre-charge voltage applied to the gate of the complement differential transistor;
• a means for discharging the capacitor circuit onto the gate of the differential transistor to couple the NV memory circuit to the ground node to discharge the pre-charge voltage on the gate of the differential transistor to a threshold voltage of the differential transistor, and a means for discharging the complement capacitor circuit onto the gate of the complement differential transistor to couple the complement NV memory circuit to the ground node to discharge the complement pre-charge voltage on the gate of the complement differential transistor to a complement threshold voltage of the complement differential transistor, to substantially cancel offset voltages of the differential transistor and the complement differential transistor;
• a means for pre-charging an output node to a ground voltage on the ground node coupled to the complement NV memory circuit, and a means for pre-charging a complement output node to the ground voltage on the ground node coupled to the NV memory circuit;
• and
• a means for applying the supply voltage to the NV memory circuit to generate a read current through the NV memory circuit based on a resistance of the NV memory circuit to generate a complement output voltage on the complement output node to activate the complement differential transistor, and a means for applying the supply voltage to the complement NV memory circuit to generate a complement read current through the complement NV memory circuit based on a resistance of the complement NV memory circuit to generate the output voltage on the output node to activate the differential transistor, such that the output voltage on the output node represents a difference in resistance between the NV memory circuit and the complement NV memory circuit, wherein the complement output voltage on the complement output node represents a difference in resistance between the complement NV memory circuit and the NV memory circuit.

A method of sensing a differential voltage based on a difference in stored memory states in a non-volatile (NV) memory circuit and a complement NV memory circuit, comprising:

• pre-charging a first gate of a differential transistor to a pre-charge voltage based on a supply voltage coupled to a supply node, the differential transistor coupled between an NV memory circuit and a ground node, and pre-charging a second gate of a complement differential transistor to a complement pre-charge voltage based on the supply voltage coupled to the supply node, the complement differential transistor coupled between a complement NV memory circuit and the ground node;
• pre-charging a capacitor circuit coupled between the gate of the differential transistor and the ground node based on the pre-charge voltage applied to the gate of the differential transistor, and pre-charging a complement capacitor circuit coupled between the gate of the complement differential transistor and the ground node based on the complement pre-charge voltage applied to the gate of the complement differential transistor;
• discharging the capacitor circuit onto the gate of the differential transistor to couple the NV memory circuit to the ground node to discharge the pre-charge voltage on the gate of the differential transistor to a threshold voltage of the differential transistor, and discharging the complement capacitor circuit onto the gate of the complement differential transistor to couple the complement NV memory circuit to the ground node to discharge the complement pre-charge voltage on the gate of the complement differential transistor to a complement threshold voltage of the complement differential transistor, to substantially cancel offset voltages of the differential transistor and the complement differential transistor;
• pre-charging an output node to a ground voltage on the ground node coupled to the complement NV memory circuit, and pre-charging a complement output node to the ground voltage on the ground node coupled to the NV memory circuit;
• and
• applying the supply voltage to the NV memory circuit to generate a read current to flow through the NV memory circuit based on a resistance of the NV memory circuit to generate a complement output voltage on the complement output node to activate the complement differential transistor, and applying the supply voltage to the complement NV memory circuit to generate a complement read current to flow through the complement NV memory circuit based on a resistance of the complement NV memory circuit to generate an output voltage on the output node to activate the differential transistor, such that the output voltage on the output node represents a difference in resistance between the NV memory circuit and the complement NV memory circuit, the complement output voltage on the complement output node represents a difference in resistance between the complement NV memory circuit and the NV memory circuit.

A non-volatile (NV) memory circuit, comprising:

• a latch circuit, comprising:
• a latch input configured to receive an input data signal;
• and
• a latch output;
• the latch circuit configured to latch input data based on the received latch input data signal and generate an output data signal on the latch input based on the latch input data;
• a sensing circuit, comprising:
• a differential amplifier, comprising:
• an output node configured to receive an output voltage;
• a complement output node configured to receive a complement output voltage;
• a differential transistor comprising a first gate, a first node, and a second node coupled to a ground node;
• a complement differential transistor comprising a second gate, a third node, and a fourth node coupled to the ground node;
• a pre-charge control circuit coupled between the first gate and the output node, the first pre-charge control circuit configured to be activated to couple the first gate to the output node;
• a complement pre-charge control circuit coupled between the second gate and the complement output node, the complement pre-charge control circuit configured to be activated to couple the second gate to the complement output node;
• a ground control circuit coupled between the ground node and a capacitor node;
• a complement ground control circuit coupled between the ground node and a complement capacitor node;
• a capacitor circuit coupled between the first gate and the capacitor node;
• and
• a complement capacitor circuit coupled between the second gate and the complement capacitor node;
• the NV memory circuit coupled between the complement output node and a supply node, the NV memory circuit configured to store a memory state;
• a complement NV memory circuit coupled between the output node and the supply node, the complement NV memory circuit configured to store a complement memory state complementary to the memory state;
• and
• a differential amplifier control circuit coupled to a supply voltage node configured to receive a supply voltage and the supply node;
• and
• a write circuit coupled to the latch output, the output node, and the complement output node, configured to receive the latch input data, the write circuit configured to write a write output signal based on the output data signal to the output node to be stored in the NV memory circuit, and write a complement write output signal, complementary to the write output signal, based on the output data signal to the complement output node to be stored in the complement NV memory circuit.