Semiconductor memory device, and signal line layout structure thereof

A memory device comprising:

• first and second memory blocks, each including a memory cell array, a sub-word line drive region and a bit line sense amplifier region corresponding to the memory cell array;
• first and second data transmission lines disposed and extending on an identical row in the bit line sense amplifier region of the memory cell array, wherein the first and second data transmission lines transmit data of the memory cell array of the memory block;
• a row decoder configured to select one of the first and second memory blocks in response to a row address and enable a word line of the memory cell array included in the selected memory block;
• a column decoder configured to generate, in response to a column address, first and second column select signals corresponding to the first and second data transmission lines of the bit line sense amplifier region of the memory cell array included in the selected memory block;
• and
• a sense amplifier driver comprising:
• a drive signal generation unit configured to generate first and second drive signals respectively corresponding to first and second bit line sense amplifiers by combining a bit line sense amplifier enable signal with the first and second column select signals, and
• a drive unit configured to provide power line signals to the first and second bit line sense amplifiers in response to the first and second drive signals, respectively.